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vhdl

Width mismatch vhdl at constant declaration


I really don't get it. It's a simple constant vector declaration.

If it's a vector, shouldn't it be allowed to have any value (3 in my case)?

Error:

  Width mismatch, location has width 2, value 3

At code:

    constant s0: std_logic_vector := "000";

Solution

  • It turned out that the problem was elsewhere in the code where I tried to calculate with a vector of wrong width. The problem was that the error was reported at the constant declaration and not at the place of error