Search code examples
syntaxvhdl

VHDL-parse error, unexpected GENERIC, expecting END

I have a piece of code in vhdl:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity UartTX is


    port(clk,reset,tx_start,s_tick:in std_logic;
            datain : in std_logic_vector(7 downto 0);
            tx_done : out std_logic;
            tx:out std_logic);

    generic(DBITS : integer := 8; SB_TICK : integer := 16);

end UartTX;

architecture Behavioral of UartTX is

type tx_state is (idle,start,data,stop);

begin


end Behavioral;

While checking for syntax in Xilinx ISE 10.1, the error

parse error, unexpected GENERIC, expecting END

is coming related to the

generic

part of entity declaration. What would be the reason?

Solution

  • The generic clause must be before port clause, so just move the generic clause up inside entity.