VHDL program - Signal do not advance in if statement

Question

I wrote this following program

library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;

ENTITY LOGIC IS 
    PORT(
        clk        :     IN std_logic;      
        rst        :    IN std_logic
        );
END LOGIC;


ARCHITECTURE LOGIC_ARC OF LOGIC IS

type rom_table is array (256 downto 0) of std_logic_vector(7 downto 0);
signal Mem112: rom_table  := (others => (others => '0'));

signal wr      :     std_logic := '0';
signal En      :     std_logic :='1'; 

signal CurrentAdd1                    :   std_logic_vector(6 downto 0) := "0000010";
signal CurrentAdd2                    :   std_logic_vector(6 downto 0) := "0000010";
signal CurrentAdd2Before              :   std_logic_vector(6 downto 0);
signal CurrentAdd2Before2             :   std_logic_vector(6 downto 0);
signal RegAdd1Before, RegAdd1Before2  :   std_logic_vector(6 downto 0);
signal RegAdd1                        :   std_logic_vector(6 downto 0) := "0000010";


signal RegData1, RegData2  :  std_logic_vector(7 downto 0);
signal WrData1             :  std_logic_vector(7 downto 0);


signal Delay1  :  std_logic_vector(2 downto 0) := "000";
signal Delay2  :  std_logic_vector(1 downto 0) := "00";

signal check1, check2   :  std_logic := '0';
signal zero  :  std_logic := '0';

signal Q1, Q2  :  std_logic := '0';
signal start2  :  std_logic := '0';


BEGIN

P0: process
    begin
        wait until rising_edge(clk);        
        if (Q1 = '1') then 
            En <= '0';
        --  Q1 <= '0';
            start2 <= '1';
        elsif (Q2 = '1') then
            En <= '1';
        --  Q2 <= '0';
        else
            start2 <= '0';
        end if;
    end process;


P1: process
    begin   
        wait until rising_edge(clk);
            if ((En = '0') and (Q2 = '0')) then
                check1 <= '1';  --DELETE
                CurrentAdd2 <= CurrentAdd2 + 1;
                CurrentAdd2Before <= CurrentAdd2;
                CurrentAdd2Before2 <= CurrentAdd2Before;

                RegData2 <= Mem112(conv_integer(CurrentAdd2));
                if (Delay2 < "11") then
                    Delay2 <= Delay2 + 1;
                end if;

                if (Delay2 > "01") then
                    if (RegData2 = "00000000") then
                        Q2 <= '1';
                        Delay2 <= "00";
                        CurrentAdd1 <= CurrentAdd2Before;
                        CurrentAdd2 <= CurrentAdd2Before;
                    end if;
                end if;
            else
                Q2 <= '0';
            end if;  
    end process;



P2: process
    begin
        wait until rising_edge(clk);
            if ((En = '1') and (Q1 = '0')) then
                check2 <= '1';  --DELETE
                if (start2 = '1') then
                    RegAdd1 <= "0000000";
                    check2 <= '0';
                else
                    RegAdd1 <= CurrentAdd1 + RegAdd1;               
                end if;

                RegAdd1Before <= RegAdd1;
                RegAdd1Before2 <= RegAdd1Before;

                if (wr = '1') then
                    Mem112(conv_integer(RegAdd1Before2)) <= WrData1;
                end if;
                RegData1 <= Mem112(conv_integer(RegAdd1));      

                WrData1 <= RegData1 + 1;

                    if (Delay1 < "100") then
                    Delay1 <= Delay1 + 1;
                end if;

                if (Delay1 > "001") then
                    wr <= '1';
                end if; 

                if (Delay1 > "011") then
                    if (RegAdd1 > "1110000") then
                        wr <= '0';
                        Q1 <= '1';
                        Delay1 <= "000";
                    end if;
                end if;
            else
                Q1 <= '0';
            end if;
    end process;    

END LOGIC_ARC;

but in P2 when the line

if (start2 = '1') then

is true, the signal RegAdd1 do notr change to what i want (0), it just continue from is last value to the next clock.
what could cause the problem?.
(i upload the whole program because i didnt know if there is a diffrent code that cause the problem).
Thanks in advance,
Gal

Answer 1

The code with:

RegAdd1 <= "0000000";

is never executed, since the guarding condition is never true, so this expression is always false:

(En = '1') and (Q1 = '0') and (start2 = '1');

You can see that by inserting some debug code like:

signal tbd : boolean;
...
process (clk) is
begin
  if rising_edge(clk) then
    tbd <= (En = '1') and (Q1 = '0') and (start2 = '1');
  end if;
end process;