Piggybacking to UVM error

Is there an easy way to piggy back a custom function to UVM_ERROR macro without manipulating the UVM library ?(i.e whenever a UVM error is invoked anywhere in the environment I want my function to be called along with it.)

Solution

Haven't yet tried this myself, but the uvm_report_catcher looks like it does what you want.

It's a callback that you can implement whenever a uvm report (like a UVM_ERROR) is about to be issued, and your function gets called before it gets reported.

Example is available here, section 4.9.3: http://low-powerdesign.com/article_Cadence-UVM_101810.html

Output not updated as expected
How to add all, except one file in iverilog command line instruction from a folder?
Verilog module not being called
Static vs. automatic tasks
Xilinx Vivado 2023 IP block design issue: Unable to connect output of RTL module to AXI GPIO output that is connected to LED
Why do I get a syntax error using the ternary operator with function calls?
Constraint to randomize such a way that consecutive 2 bits are set to 1, other bits are 0 for 16-bit variable
Verilog port mapping when a gate netlist module's vector ports instatantiated inside an rtl module have been split into each bit by P&R tool
What is the best practice to handle invalid or illegal combinations of inputs in a verilog module?
Verilog slice direction differs from VHDL
Systemverilog/Verilog VCP2000 “Syntax error. Unexpected token: class[_IDENTIFIER].”
Verilator, running simulator gives: Invalid argument
How to compile and run a single verilog file with Questa?
Use loop to access generated modules
Parity checker in verilog only calculates a result once
How to check signal drive strength?
Variable scope verilog: Why does $display inside the task print the global variable sig and not the local variable sig that was declared within task
Array of wire OR-reduction is wrong
Random constraints on array of structure elements
$dumpfile and $dumpvars not working in vscode. Error in terminal says requires SystemVerilog
How to select bits in expression?
D-type Flip Flop - Behavioral vs Gate-Level Modeling in Verilog, Timing of state transitions
What's the best way to tell if a bus contains a single x in Verilog?
Not getting the full Timing Report in Synthesis Report
Reducing OR not working as expected when bit slicing in a loop
SystemVerilog testbench: Making an array of logic with run-time determined width
Modules compiling to 0 gates
Why does blocking vs. non-blocking matter in this Verilog snippet?
How can I schedule multiple inputs into an instantiated SystemVerilog module?
How can I declare an output of a module to be a decimal number instead of a single bit?