Can we include delays in structural architecture?

Question

I am trying to simulate EXOR using NOR gates. I have written the following logic for EXOR gate. Now, my nor2 is defined with 4 ns delay.

ENTITY ex IS
    PORT (a, b : IN BIT; c : OUT BIT);
END ex;

ARCHITECTURE structure OF ex IS

    SIGNAL tmp1, tmp2, tmp3, tmp4: BIT;
    COMPONENT nor2 PORT (x, y : IN BIT; z : OUT BIT); END COMPONENT;
BEGIN

    u0: nor2 PORT MAP (a, a, tmp1);

    u1: nor2 PORT MAP (b, b ,tmp2);

    u2: nor2 PORT MAP (tmp1,tmp2,tmp3);

    u3: nor2 PORT MAP (b, a, tmp4);

    u4: nor2 PORT MAP (tmp3, tmp4, c);

END structure;

I know that tmp1, tmp2 and tmp4 will change signals after 4 ns after a or b changes. I also notice that tmp3 and hence c change after 4 ns (because nor2 has 4 ns delay[c <= a nor b after 4ns]). But I want tmp3 to reflect the change after 8 ns as per the proper logic and c after 12 ns. This will give me the proper output for EXOR. My question is how do I introduce a delay in structural architecture? Is there a way to do it? I tried to search but did not find any and wait doesn't work, it keeps giving me syntax error (wait for 8ns). Thanks a lot for the help!

Answer 1

There is nothing wrong with the simulation result. It seems wrong because nor is a short-circuit operator.

Suppose that

a = '0'
b = '1'

then

tmp1 = '1' (a nor a)
tmp2 = '0' (b nor b)
tmp4 = '0' (b nor a)
tmp3 = '0' (tmp1 nor tmp2)
c    = '1' (tmp3 nor tmp4)

Now b changes to '0',

tmp1 = '1' remains unchanged
tmp2 = '1' after 4 ns
tmp4 = '1' after 4 ns
tmp3 = '0' remains unchanged (regardless of b because of short-circuit evaluation)
c    = '0' after 8 ns (not 12 ns because it only waits for tmp4 in this case)