makefile double dollar sign in user defined function

In chapter 8 (P150) of Managing Projects with GNU Make, the author introduces Tromey’s Way.

define make-depend
  $(CC) $(CFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -M $1 | \
  $(SED) 's,\($$(notdir $2)\) *:,$$(dir $2) $3: ,' > $3.tmp
  $(MV) $3.tmp $3
endef

%.o: %.c
    $(call make-depend,$<,$@,$(subst .o,.d,$@))
    $(COMPILE.c) -o $@ $<

My understanding of double dollar sign, $$(notdir $2) and $$(dir $2), is that it is used to escape $ so that it's expanded later. However, we are expect it to operator on $2 in here, right?

I suspect it's one error, but I couldn't find it on errata. Is it really one mistake, or I misunderstood it?

Solution

Yes, used like this it's an error to double the dollar signs. The only time it wouldn't hurt to double them is if you were going to send the results of the call function to something like eval which expand the results again. But there's no need for it in either case.

I should point out that this example, while better than most other methods, is somewhat deprecated these days. The GCC compiler has options which can generate pretty much exactly the makefile dependency output you want without postprocessing, and while still creating the object file at the same time. This is actually significantly more efficient because you don't have to run the compiler twice every time you compile.