VHDL - determining the range of a 2d array

Question

I have two 2D arrays:

type array1x1D is array (0 to 10) of std_logic_vector(0 to 10); -- Array of arrays
type array2D is array (0 to 10, 0 to 10) of std_logic; -- Real 2D array

How do I access the range of the std_logic_vectors in the former and the range in the latter? I could of course use a variable to keep track of their size but I would prefer to avoid that. I am trying to loop over the arrays using GENERATE statements.

Answer 1

array1x1D:

VHDL-2002: A subtype is required for the std_logic_vector(0 downto 10) if you want to get the range of this part, thus splitting the type into:

subtype array1x1D_element is std_logic_vector(0 to 10);
type array1x1D is array (0 to 10) of array1x1D_element; -- Array of arrays

Then you can do array1x1D_element'range.

VHDL-2008: Use the added 'element attribute (probably for that purpose :-), and write array1x1D'element'range.

array2D:

Access the different dimensions through an index to 'range, thus with array2D'range(1) and array2D'range(2).