I know that its not allowed to compare with X
or Z
in a synthesizable VHDL code. But is it allowed to write a code in which I compare a signal to 0
or 1
to detect an Z
and suspend the operation? The code is as follows:
process(clk)
begin
if rising_edge(clk ) then
if(rst = '0') then
reg_0 <= (others => 'Z');
elsif(btf_start = '1') then
reg_0 <= "ZZ" & frame_in;
elsif(t_btf_finish = '1') then
reg_0 <= (others => 'Z');
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if(reg_0(0) = '0' or reg_0(0) = '1') then
-- DO SOME OPERATIONS
else
-- DO NOTHING
end if;
end if;
end process;
No, this won't work. Physical digital signals can have exactly 2 states, '0' and '1'. The states are defined by the voltage on the signal: less than some voltage is a '0', greater than that voltage is a '1'. Even floating (high-z) signals will have some voltage that will be interpreted as a '1' or '0'.
'Z' basically says that a certain source isn't driving the signal, allowing a different source to drive a '0' or '1'. For the case when no source is driving the signal, the signal will usually have a pull-up or pull-down resistor to keep it in a defined '1' or '0' state by default.