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vhdl

Flip-Flop with enable with a single cycle enable signal

I have a flip-flop that I need to enable for only one clock cycle. What is the standard practice for single-cycle enable signal in these kind of situations?

Thanks in advance

Solution

  • Flip-flop that is only enabled a single cycle after reset is shown below; all signals are std_logic:

    process (clk, rst) is
begin
  if rst = '1' then
    fired <= '0';
  elsif rising_edge(clk) then
    if fired = '0' then
      q     <= d;
      fired <= '1';
    end if;
  end if;
end process;