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verilogtimedelay

How to include time delay in synthesized verilog?

I am trying to write a synthesizable code in verilog, in which I require to include a time delay of few seconds. I have done the simulation using #delay, but this is not acceptable by synthesizer.

In the process of synthesizing a FSM, which change its states not based on some condition but after few seconds of time delay, I want the above time delay method. FSM has to switch states say from state_1 to state_2 after 4 seconds and state_2 to state_3 after 2 seconds and so on.

Solution

  • For switching the states after a time delay,I hope this code helps.

    current_state=state_1;
    for(i=0;i<=timedelay*freq;i=i+1)
    @posedge;
    current_state=state_2;