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timestampautomated-testsvhdl

Get current timestamp VHDL

In order to create a random seed, I would like to get the system timestamp in my VHDL testbench.

How can I do that?

By the way, I'm using the RandomPkg from the OSVVM library

Regards.

Solution

  • For a generic VHDL approach, you can pass the system time as generic to the test bench entity. If the test bench looks like:

    entity seed_tb is
  generic(SEED : natural := 0);
end entity;

architecture sim of seed_tb is
begin
  assert FALSE report "SEED = " & integer'image(SEED) severity NOTE;
end architecture;

    Then on Linux with the ModelSim simulator, the command lines for compile and run can be:

    > vlib work
> vcom seed_tb.vhd
> vsim seed_tb -c -gSEED=`date +%s` -do "run; exit"

    The date +%s give seconds since 1970-01-01, which will fit in the VHDL natural type (even for another 25 years :-).

    The approach has the advantage that it is easy to rerun the simulation with the same seed from the command line, in case debugging is necessary.