Adressing a specific bits in an array of std_logic vector in VHDL

Question

Im new to VHDL. my problem is that i cant seem to find the correct syntax for writing or reading from an array of std_logic_vector. i init the array as such :

 TYPE eleven_samples_in IS ARRAY ( 0 TO 10 ) OF STD_LOGIC_VECTOR( 87 DOWNTO 0 );

and i try addressing it as such :

odd: for i in 1 to 6 generate
   node: compare_level
       port map(
                input  => eleven_samples_in(i*2 - 1)(79 DOWNTO 0),
                output  => eleven_samples_out(i*2 - 1)(79 DOWNTO 0 )
               );
end generate odd;

Or :

 port map(
           input  => eleven_samples_in(i*2 - 1,79 DOWNTO 0),
           output  => eleven_samples_out(i*2 - 1,79 DOWNTO 0 )
         );
 end generate odd;

But i get an Errors such as :

Error (10409): VHDL Type Conversion error at Median_Filter.vhd(45): converted type of object near text or symbol "eleven_samples_in" must match std_logic_vector type of target object

I searched the web and found nothing that works.

thank you very much for the help .

Answer 1

you create a type eleven_samples_in, and use that directly. This is incorrect.

Instead:

type eleven_samples_in_type is array (0 to 11) of std_logic_vector(89 downto 0);
signal eleven_samples_in : eleven_samples_in_type;

...

Without knowing anything about your compare_levels component, thats as much help as I can be