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castingintegervhdl

Parsing std_logic_vector to integer

If I convert two std_logic_vector with values 1 and 0 respectively

signal mlx, mtx : std_logic_vector(15 downto 0)

into a integer through

variable WLX : integer;
variable WTX : integer;

WLX := TO_INTEGER(signed(mlx));
WTX := TO_INTEGER(signed(mtx));

and after that compare the subtraction of these with -1 literal:

if WTX-WLX = -1

The result will be true?

Thanks

Solution

  • If mlx=X"0001" and mtx=X"0000", then yes, subtracting mlx from mtx as integers yields -1, so given the question the answer is yes.

    However: casting values to an integer in order to operate on them or compare them is usually a sign of poorly written code.

    Why don't you just use signed for mlx and mtx, and avoid the use of integers?

    architecture arch of ent is
    signal mlx, mtx : signed(15 downto 0);
begin
    process(clk) begin
        if(rising_edge(clk)) then
            if(mtx - mlx = -1) then
                -- Do what needs to be done.
            end if;
        end if;
    end process;
end architecture;