Issues with indexing arrays in VHDL

Question

I have an assignment to create a simple microprocessor in VHDL. My code looks like this

architecture Behavioral of uc is

type instruction_t is array (255 downto 0) of std_logic_vector (15 downto 0);

constant LOAD : std_logic_vector(7 downto 0) :=x"01";
--some more instruction codes defined

signal PC : std_logic_vector (7 downto 0); -- program counter

signal cur_inst : std_logic_vector (15 downto 0);

constant ROM :
instruction_t :=
(
(LOAD & x"07"),
(ADD & x"05"),
-- some more code goes here
others => x"0000"
);

begin

process (CLK, RESET) is
    begin
        if RESET = '1' then
            -- do stuff
        elsif rising_edge(CLK) then
            cur_inst <= ROM(conv_integer(PC));
            PC <= PC + 1;
            -- some other stuff
        end if;
    end process;
end Behavioral;

The problem I have is with this part:

cur_inst <= ROM(conv_integer(PC));

because simply nothing happens - cur_inst is always zero. I tried using

cur_inst <= ROM(to_integer(unsigned(PC));

but result is the same - I get nothing. PC is incremented properly, but I cannot read anything from ROM array. I also tried defining PC as unsigned or integer, but result is the same. What am I doing wrong?

Answer 1

Since you are defining instruction_t as an array(255 downto 0), initializing the array may be occuring in the opposite order that you intended.

(LOAD & x"07") will be assigned to ROM(255), (ADD & x"05") will be assigned to ROM(254), etc.

Define the type instruction_t as an array (0 to 255) to avoid this problem.