VHDL : signal initialisation

I'm a beginner at VHDL and I have problems when to decide whether I should initialize my signal or not...

Here's an exemple :

            entity tatoo is 
            port (
            clk, reset : in std_logic;  
            opcode : in std_logic_vector(2 downto 0); 
            A, B : in std_logic_vector(3 downto 0);
            F : out std_logic_vector(3 downto 0)
            ); 

            architecture toota of tatoo is 
            signal Q : std_logic_vector(3 downto 0);

            begin

            process (clk, reset) -- register for F
            begin
                if(reset = '1')
                    then F <= "0000";
                elsif(Clk'event and Clk = '1')
                    then F <= Q;
                end if;
            end process;

            process(opcode, A, B) -- ALU
            begin

Should I initialize Q here ? => Q <= "0000"; ?

                case opcode is 
                    when "00" =>
                        Q <= "0000";
                    when "01" =>
                        Q <= A-B;
                    when "10" => 
                        Q <= B-A;
                    when "11" =>
                        Q <= A xor B;
                end case;
            end process;

Thanks a lot,

Solution

You need to initialise it somewhere, or you'll get a latch. Your suggestion is fine (though Q <= (others => '0') is more future-proof), of you could have a default/others branch in the case statement, where you give Q a default value. Basically, when you have a combinatorial process like this one, make sure that anything your drive always has a defined value whatever the value of the inputs may be. If not, you're inferring memory of some sort.