VHDL - Why is this signal never driven low?

Question

I hope you can help me!

I'm writing a program for a Spartan 3E prototype board which will calculate the frequency of a sinusoidal input signal. Due to issues with the ADC I'd chosen to use, I decided to generate this signal internally, simulating the input from the ADC. My problem now lies in the module responsible for retrieving the data from the simulated ADC.

The full system simulates as expected, however, on synthesis a large number of warnings are generated. These were all traced back my chip select signal, which is supposed to be driven low at roughly 16KHz. The odd thing was that the synthesis tools did not generate a warning, only an info for the fact that the chip select is constantly high.

This is the info that is generated on synthesis:

Xst:2679 - Register <int_CS> in unit <DataRetrieval> has a constant value of 1 during circuit operation. The register is replaced by logic.

This is the module in question:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity DataRetrieval is
Port ( Reset : in  STD_LOGIC;
 C16MHz : in  STD_LOGIC;
       D_in : in  STD_LOGIC;
       CS : out  STD_LOGIC;
       D_clk : out  STD_LOGIC;
       Sample : out STD_LOGIC_VECTOR(7 downto 0));
end DataRetrieval;

architecture Behavioral of DataRetrieval is

signal bit_counter : Integer range 0 to 15;
signal D_reg : STD_LOGIC_VECTOR(15 downto 0);
signal clkDivide : Integer range 1 to 500;
signal int_CS : STD_LOGIC;
signal int_D_clk : STD_LOGIC;
signal edgeBit : STD_LOGIC;

begin

process (Reset, C16MHz, D_in, bit_counter, clkDivide, int_CS, edgeBit, int_D_clk)
begin
    if Reset = '1' then 
        clkDivide <= 1;
        bit_counter <= 15;
        D_reg <= (others => '0');
        Sample <= (others => '0');
        int_CS <= '1';
        edgeBit <= '0';
        int_D_clk <= '0';
    elsif rising_edge(C16MHz) then
        clkDivide <= clkDivide + 1;
        int_D_clk <= not int_D_clk;--8MHz data clock
        if clkDivide = 1000 then
            D_reg <= (others => '0');
            bit_counter <= 15;
            clkDivide <= 1;
            int_CS <= '0'; -- CS driven low here in order to allow time for conversion
        else
            if int_CS = '0' then
                if bit_counter = 0 then
                    D_reg(bit_counter) <= D_in;
                    int_CS <= '1';--disables ADC
                    Sample <= D_reg(11 downto 4);
                else
                    if edgeBit = '0' then
                        edgeBit <= '1';
                        D_reg(bit_counter) <= D_in;
                        bit_counter <= bit_counter - 1;
                    else
                        edgeBit <= '0';
                    end if;
                end if;
            end if;
        end if;
    end if;
end process;

 CS <= int_CS;
 D_clk <= int_D_clk;

end Behavioral;

The module uses the 16MHz clock to get data from the simulated ADC, by generating a data clock at 8MHz. The clock divide signal is a counter which decreses the clock speed to 16KHz, which drives the chip select low at the end of each count, then high once all the data has been retrieved for one sample.

According to the synthesis tools, CS is never driven low and is therefore trimmed, which means none of the rest of the system functions. The module does not synthesise correctly on its own, but it does simulate.

Any input on this issue would be greatly appreciated.

Thanks

Answer 1

You declare

signal clkDivide : Integer range 1 to 500;

and then check

if clkDivide = 1000 then

The synthesis tool probably instantiates a 9-bit register for clkDivide which can never reach the value 1000. Try changing the integer range to 0 to 1024 or similar.