Mealy and Moore implementations in verilog
Can any one tell what are the differences between these implementations in verilog/VHDl? I mean how does Mealy and Moore Synthesize into circuits in detail ? Any links would prove useful too.
I am quite familiar to this
Thank you
But is this the way it implements ??
The synthesiser will implement logic that matches the code you have written. If you have outputs which are unregistered (ie, not written to from a clocked block) then that's what the synthesiser will give you.
More to the point - why does anyone care? Academics seem to keep teaching Mealy vs Moore for no good reason I can see. In my getting on for 2 decades of professional electronic design, I have never had to care what "kind" of state machine I am getting. I just describe the behaviour and let the tools produce the circuits. The tools also do not care (check the logfiles, it won't say "found a Mealy state-machine" anywhere).
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