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architecturearmprocessorcpu-registers

ARM CPSR - 5 bits for mode?

I'am learning about the arm architecture.
1. I figured that the CPSR had 5 bits allocated to specify the current mode it is executing in. where as we only have about 6-7 different modes for which 3 bits would have sufficed. why then do we have 5 bits for the same?
2. What is the difference between system/supervisor mode? which mode does the OS execute it's code in?
3. Also I want to know whether it is possible to switch from user mode to system/supervisor mode, manually with out a swi call etc. what would restrict me from doing this?
4. And when I switch to the supervisor mode how do i use the user mode register along with the banked register that already exist for that mode?

Solution

    1. Why compress the current mode into as few bits as possible? Perhaps the designers felt that design of the ARM was cleaner if the mode bits were more spread out. Besides, it's not like there's a shortage of spare bits in the CPSR.

      However, you might notice that all 8 modes listed here have bit 4 set to 1. This is because ARM6 (and ARM7?) processors support four additional '26-bit' modes for compatibility with ARM2/ARM3 code. These four 26-bit modes have bit 4 set to 0, and are versions of user, IRQ, FIQ and supervisor mode that emulate ARM2/ARM3 behaviour. In the ARM2/ARM3, there is no CPSR nor SPSR, the N, Z, C, V, I and F flags are in the top six bits of the PC and the processor mode is in the bottom two bits of the PC. As the 26-bit modes are not listed in the article I linked to above I can only assume they are not supported in later ARMs.

    2. Supervisor and system modes are different, see the list in the linked article above. As for which mode is used by the OS, that depends on the OS. In the old days before system mode came along, supervisor mode would have been used. I can't say whether the advent of system mode has changed this.

    3. I believe that there is no way to switch from user mode to supervisor mode without using a SWI. This is intentional, it's a security/stability feature that prevents processes without suitable privileges from causing system instability by accessing memory locations they should not be able to.

    4. Why do you want to use banked user-mode registers from supervisor mode? The only user-mode registers you can't get hold of from supervisor mode are R13 and R14.