VHDL error related to concatenation of variable

Question

I am writing VHDL code in which I have used tempx and tempz as variables and tried to concatenate them, but I am having some errors on the line annotated below. Suggestions on what to do please?

The errors are:

Error (10500): VHDL syntax error at ArrayDivider.vhd(53) near text ":=";  expecting "(", or "'", or ".",
Error (10500): VHDL syntax error at ArrayDivider.vhd(53) near text "&";  expecting "(", or "'", or "."

Code:

------- Array Divider --------

library ieee;
use ieee.std_logic_1164.all;

----- Entity -----

entity ArrayDivider is
    generic
    (
        ---- For x/y
        Nx : integer := 8; --- Number of bits in x
        Ny : integer := 4  --- Number of bits in y
    );
    port
    (
        ipx : in std_logic_vector(Nx-1 downto 0); -- Input x --- (Nx-1 downto 0)
        ipy : in std_logic_vector(Ny-1 downto 0); -- Input y --- (Ny-1 downto 0)
        opd : out std_logic_vector(Nx-Ny downto 0); -- Quotient --- (Nx-Ny downto 0)
        opr : out std_logic_vector(Ny-1 downto 0) -- Remainder --- (Ny-1 downto 0)
    );
end ArrayDivider;

----- Architecture -----

Architecture Div of ArrayDivider is
--- This component will compare ipy with parts of ipx of given bits and ---
--- generate bits of divident as well as partial subtraction results ---
--- x = parts of ipx (tempx), y = ipy, op = opd(x) and final z = opr ---    

    component Cmp is
        generic
        (
            N : integer := 4
        );
        port
        (
            x : in std_logic_vector(N-1 downto 0); --- N-1 downto 0
            y : in std_logic_vector(N-1 downto 0); --- N-1 downto 0
            z : out std_logic_vector(N-1 downto 0); --- N-1 downto 0
            op : out std_logic
        );
    end Component;
    variable tempx : std_logic_vector(Ny-1 downto 0) := ipx(Nx-1 downto Nx-Ny); --- (Ny-1 downto 0) (Nx-1 downto Nx-Ny)
    variable tempz : std_logic_vector(Ny-1 downto 0); --- (Ny-1 downto 0)
begin
    lup:
        for a in Nx-Ny downto 0 generate --- Nx-Ny downto 0
        begin           
    Cmpa:   Cmp generic map(Ny) port map(tempx, ipy, tempz, opd(a)); --- (Ny)
    grea:   
            if(a > 0) generate
                tempx := tempz(Ny-2 downto 0) & ipx(a-1); --- (Ny-2 downto 0)
            end generate grea;  
    zero:   
            if(a = 0) generate
                opr <= tempz;
            end generate zero;
        end generate lup;
end Div;

Answer 1

as you are not using a process, you should use signals instead of variables for tempx and tempz. your line 53 must then look as follows:

tempx <= tempz(Ny-2 downto 0) & ipx(a-1);

however, probably the use of a process makes more sense. then you have to implement your cmp component as a procedure (not done in example below). the process could look as follows:

   ...
end Component;
begin

div_proc: process(ipy, ipx)
    variable tempx : std_logic_vector(Ny-1 downto 0) ; 
    variable tempz : std_logic_vector(Ny-1 downto 0); 
begin
    lup:
        for a in 1 downto 0 loop         
    -- Cmpa:   Cmp generic map(Ny) port map(tempx, ipy, tempz, opd(a)); 
        grea:   
            if(a > 0) then
                tempx := tempz(Ny-2 downto 0) & ipx(a-1);
            end if;  
        zero:   
            if(a = 0) then
            opr <= tempz;
            end if;
    end loop;
end process div_proc;
...