I am working on a project in VHDL that will be placed onto the spartan 6 fpga. The code is ready but I am not sure how to proceed with getting it onto the fpga.
I have access to another project and noticed that this project has a Microblaze processor (.xmp) file in it and a ucf file that defines all the "NET" interfaces.
Eventually I will be using the FPGA and add-on board connector to communicate with a piece of hardware but I need moving everything onto the FPGA.
Some resources and tutorials would be great, especailly how to get the microblaze processor into my project, that is if I even need it.
Thanks
Update: I started simulation of my project and have an error.
Line 214: statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition
I get this in one of my project files in ana if statement that says
if rising_edge(clk) then
-- other if statements that assign output values
end if
I tried changing the code around but it no longer works if I do.
Not sure what the error means exactly.
The UCF file should contain both constraints to which pins that belong to each of your signals as well as any timing conditions. The "easiest" way is to read the guide for writing such files, or to use the built-in tool that helps you to get them right
Here is the Xilinx guide.
Thiis is one of the most important constraints:
TIMESPEC “TSidentifier”=PERIOD “TNM_reference” period {HIGH | LOW} [high_or_low_time ] INPUT_JITTER value; (cut from the above file)