Error testing 8-bit LFSR written in VHDL

Question

I'm a first time user so please bear with me.

Part of a simple game we have to make for an assignment involves writing a pseudo-random number generator in the form of an 8-bit LFSR. I am writing my code using Xilinx ISE, my notes and a sample code provided here:

http://www.oocities.org/siliconvalley/screen/2257/vhdl/lfsr/lfsr.html

Now the code does synthesize but gives me warnings concerning the sensitivity list. When I run the test bench, however, I get all U values for the pseudo_rand. I realize that this random number generator will be internal so there shouldn't be an output but when I write the code with the pseudo_rand as a signal (that variant is currently commented out,) it does not show up in simulation.

Below is the code for the LFSR followed by the code for the corresponding test bench:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity LFSR_3_16_2013 is
port(       clk:            in  std_logic;
            rst:            in  std_logic;
            pseu_rand:  out std_logic_vector(7 downto 0));
end LFSR_3_16_2013;

architecture Behavioral of LFSR_3_16_2013 is
--signal        clk:            std_logic;
--signal        rst:            std_logic;
signal          seed:           std_logic_vector(7 downto 0):= "10000000";
signal          biffer:         std_logic_vector(7 downto 0); 
--signal        pseu_rand:      std_logic_vector(7 downto 0);

begin

lfsr : PROCESS(clk,rst)
begin
    if(rst='0') then
    --pseu_rand <= seed;

    biffer      <= seed;
    pseu_rand   <= biffer; 

    elsif (clk'event and  clk='1') then 
    --pseu_rand(0)              <= pseu_rand(7) xor pseu_rand(6);                      
    --pseu_rand(7 downto 1)     <= pseu_rand(6 downto 0); 

    biffer(0)                   <= biffer(7) xor biffer(6);                      
    biffer(7 downto 1)          <= biffer(6 downto 0); 
    pseu_rand                   <= biffer;

    end if;

    end process lfsr;
end Behavioral;

And now the test bench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY LFSR_tb_3_16_2013 IS
END LFSR_tb_3_16_2013;

ARCHITECTURE behavior OF LFSR_tb_3_16_2013 IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT LFSR_3_16_2013
    PORT(
         clk       : IN  std_logic;
         rst       : IN  std_logic;
         pseu_rand : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';

    --Outputs
   signal pseu_rand : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
    uut: LFSR_3_16_2013 PORT MAP (
          clk => clk,
          rst => rst,
          pseu_rand => pseu_rand
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
      wait for 100 ns;  

      wait for clk_period*10;

      -- insert stimulus here 
      rst <= '1';

      wait;
   end process;

END; 

Any help would be greatly appreciated, I am pretty stumped.

Thanks, Yusif Nurizade

Answer 1

the sensitivity list tells the process on what actions it has to "wake up". this means, your process does only react on activity of clk or rst signal. therefore pseu_rand is all 'U's until the first clock edge appears. this is actually not a problem for synthesisable code. however, if you'd like to change that, add seed and biffer to your sensitivity list.

lfsr : PROCESS(clk,rst,seed,biffer)

btw. if you use the (commented out) signal solution, you define pseu_rand directly with seed and not over biffer... therefore it's defined in your simulation from the start!