Cannot find why value doesn't jump to expectation in the right time

Question

I have the following code :

module POLY(CLK,RESET_n,IN_VALID,IN,OUT_VALID,OUT);

input         CLK,RESET_n,IN_VALID;
input  [ 3:0] IN;
output        OUT_VALID;
output [12:0] OUT;

reg        OUT_VALID;
reg [12:0] OUT;

reg        OUT_VALID_w;
reg [12:0] OUT_w;

reg [ 1:0] COUNT_IN, COUNT_IN_w;
reg [ 2:0] COUNT_DO, COUNT_DO_w;

always @(posedge CLK or negedge RESET_n)
begin
    if(!RESET_n)
    begin
        COUNT_IN <= 2'd0;
        COUNT_DO <= 3'd0;
    end
    else
    begin
        COUNT_IN <= COUNT_IN_w;
        COUNT_DO <= COUNT_DO_w;
    end
end

always @(*)
begin
    if(IN_VALID == 1'b0)
    begin
        if(COUNT_DO == 3'd7)
        begin
            COUNT_DO_w = COUNT_DO;
        end
        else
        begin
            COUNT_DO_w = COUNT_DO + 1'b1;
        end
    end
    else
    begin
        COUNT_DO_w = 3'd0;
    end
end

Why COUNT_DO doesn't jump to 1 in 14ns?

I think that due to the sensitivity list in the second always block is COUNT_DO and IN_VALID, so at start, the reset signal trigger first always block and set the COUNT_DO = 0, which change the COUNT_DO value from high impedance to 0. So, it triggers the second always block COUNT_DO_w = 0 + 1 = 1. And , in the next postive edge clock, which trigger the first always block to do COUNT_DO <= COUNT_DO_w. But it seems to delay one clock to assign it (22ns). Why does it delay one clock?

Answer 1

At time=14ns, reset is asserted (RESET_N=0), which means COUNT_DO=0 in the 1st always block. At time t=20ns, you release reset and COUNT_DO remains at 0. At time=22ns, you have your 1st posedge CLK which assigns COUNT_DO to COUNT_DO_w. The time at which COUNT_DO changes is controlled only by the 1st always block, not the 2nd.