verilog system-verilog system-verilog-assertions

SVA (SystemVerilog Assertions) : Difference between $assertoff and $assertkill?

With SystemVerilog Assertions what is the difference between $assertoff; and $assertkill; ?

They both seem to stop the execution of the assertions.

Solution

$assertoff will stop assertions except those already in the active state.

Assertions are active once triggered and waiting to move to failed or completed. $assertoff will not stop or kill the assertions in the active state.

$assertkill will stop all assertions, moving all to state off.

From Cadence Help:

$assertoff
Suspends checking of all specified assertions until $asserton is encountered. An assertion that is already executing, including assertion action blocks, will continue executing.

$assertkill
Halts checking of all specified assertions that are currently executing, then suspends checking of all specified assertions until $asserton is encountered.
NB: Per the IEEE 1800 SystemVerilog standard, the $assertkill task has no effect on immediate assertions and non-temporal concurrent assertions, due to scheduling issues.