std_logic_vector vs. integer synthesis in Xilinx vhdl

I am working in 8 bit pixel values..for ease of coding i want to use conv_integer to convert this 8 bit std_logic_vector.is it cause any synthesise problem?is it reduce the speed of hardware...

Solution

No, integers synthesise just fine. Don't use conv_integer though - that's from an old non-standard library.

You want to use ieee.numeric_std; and then to_integer(unsigned(some_vector));

If you still want to access the bits, and treat the vector as a number, then use the signed or unsigned type - they define vectors of bits (which can still have -, Z etc.) which behave as numbers, so you can write unsigned_vector <= unsigned_vector + 1.

Vivado VHDL: attribute 'stable not implemented
What is the utility of a "clock'event" if the sensitivity list has a single signal and is tested at 1?
Why am I not able to write to/read from custom AXI lite peripheral's registers
Verilog slice direction differs from VHDL
My counter "4-digit BCD Counter" does not work well!
With the MESI protocol, a write hit also stalls the processor, right?
Compiling VHDL file with ```ghdl -a``` encountered error ```ghdl:error: installation problem: ghdl1-llvm not found```
VHDL if statement precedence
Generate read-address and write address for zig-zag scan of NxN matrix
Where to force xilinx ISE to use block-rams?
FPGA efficient (a)synchronous resets
Can an embedded configuration be used for an instance inside a generate?
Weak 'H', Pullup on inout bidirectional signal in simulation
VHDL Coding .. conversion from integer to bit_vector
Viterbi Decoder VHDL project
Timing simulation in Vivado giving an error
When should I use a function over a procedure?
VHDL-2008 to_01 conversion
Uninitialized signal value for unknown reason
Representing 2 binary digits in hex for vhdl
Convert enum type to std_logic_vector VHDL
Synthesis ERROR: [Synth 8-27] else clause after check for clock not supported
Simulation Time in Concurrent VHDL Procedures
VHDL when else interpretation
Finding source of PS2 keyboard delay
Elegant Way To Compress If/Elsif Statements into Single For Loop Statement in VHDL
VHDL Hierarchical Reference within/to Generate Statement(s)
How do I install GTKWave on Windows?
In VHDL, I have an error when slicing an unsigned result
How to get real type ratio between two time values?