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syntaxsyntax-errorvhdl

VHDL If Statement Syntax Error


I have the following code:

process(value_counter, hex5_value)
    begin
        if(value_counter <= x"0F") then
            with value_counter select hex4 <=  --error on this line
            "0111111" when x"00", 
            "0000110" when x"01", 
            "1011011" when x"02", 
            "1001111" when x"03", 
            "1100110" when x"04", 
            "1101101" when x"05", 
            "1111101" when x"06", 
            "0000111" when x"07", 
            "1111111" when x"08", 
            "1101111" when x"09",
            "1110111" when x"0A", 
            "1111100" when x"0B",
            "0111001" when x"0C", 
            "1011110" when x"0D",
            "1111001" when x"0E", 
            "1110001" when x"0F";

            hex5<="0111111";
        elsif(value_counter > x"0F") then
            with value_counter mod 10 select hex4 <=
            "0111111" when x"00", 
            "0000110" when x"01", 
            "1011011" when x"02", 
            "1001111" when x"03", 
            "1100110" when x"04", 
            "1101101" when x"05", 
            "1111101" when x"06", 
            "0000111" when x"07", 
            "1111111" when x"08", 
            "1101111" when x"09",
            "1110111" when x"0A", 
            "1111100" when x"0B",
            "0111001" when x"0C", 
            "1011110" when x"0D",
            "1111001" when x"0E", 
            "1110001" when x"0F";

            with hex5_value select hex5 <=
            "0111111" when x"00", 
            "0000110" when x"01", 
            "1011011" when x"02", 
            "1001111" when x"03",
            "1100110" when x"04", 
            "1101101" when x"05", 
            "1111101" when x"06", 
            "0000111" when x"07", 
            "1111111" when x"08", 
            "1101111" when x"09",
            "1110111" when x"0A", 
            "1111100" when x"0B",
            "0111001" when x"0C", 
            "1011110" when x"0D",
            "1111001" when x"0E", 
            "1110001" when x"0F";
        end if;
end process;

but I am getting the following error on the indicated line when running it: Error (10500): VHDL syntax error at xxx near text "with"; expecting "end", or "(", or an identifier ("with" is a reserved keyword), or a sequential statement. Anyone know what's causing this, and how I can rewrite it legally and equivalently?


Solution

  • The "correct" answer is a CASE statement within a process or "with ... select" in the combinatorial region (i.e. outside a process).

    But you would have much nicer VHDL if you created a constant array of 16 7-segment display values, and simply indexed the array :

    subtype seven_seg is std_logic_vector(6 downto 0);
    
    constant decode : array 0 to 15 of seven_seg := (
                "0111111", "0000110", "1011011", "1001111", 
                "1100110", "1101101", "1111101", "0000111", 
                "1111111", "1101111", "1110111", "1111100",
                "0111001", "1011110", "1111001", "1110001");
    
        process(value_counter, hex5_value)
            begin
                if value_counter <= x"0F" then
                    hex4 <= decode(to_integer(value_counter(3 downto 0)));
                    hex5 <= decode(0);
                -- elsif value_counter > x"0F" then  
                -- surely this "elsif" is unnecessary!
                else 
                    hex4 <= decode(to_integer(value_counter(7 downto 4)));
                    hex5 <= decode(to_integer(hex5_value(3 downto 0)));
                end if;
        end process;