I am writing a VHDL test bench for a ethernet MAC. The testbench consists of a package and an combined entity + architecture file. I want to read the ethernet frames that the testbench will send to the MAC from a binary file which I exported from wireshark.
I'm writing in VHDL 2008 and I'm using a Mentor Graphics Model Technology ModelSim ALTERA vcom 10.0d Compiler.
All solutions for reading binary data in VHDL/modelsim that I've found so far use special file formats where 1 bit of the bit_vector is represented by several bits in the file. I would like VHDL to read the binary file into 8 bit bit_vectors.
Closest I've gotten so far was using a character type file, where I can write 8 bit ASCII characters directly in binary representation.
I used to do this, but have found it more productive to write a short script (in a serious text processing language) to convert from whatever input to a real VHDL file with the data described as a constant array of a suitable datatype.
This is much easier than doing file parsing in VHDL IMHO.