Never-ending synthesis with integer incrementation

Question

I have a piece of VHDL code that compile but when I try to synthesize it I get stuck, meaning the synthesization never ends and I have in the console:

Analyzing Entity Interpretor in library work (Architecture ).

I've tried to understand why but I can't. All I know is that if I comment the line CPT_PAN <= CPT_PAN - 1; then all of sudden I can synthesize.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Interpretor is
    Port (SCAN_CODE : IN STD_LOGIC_VECTOR(7 downto 0));
end Interpretor;

architecture Behavioral of Interpretor is
Signal CPT_PAN : Integer range 0 to 255 := 0;
begin
process(SYS_CLK)
begin
if (SYS_CLK'EVENT and SYS_CLK = '1') then
    if SCAN_CODE = "01101011" then 
        if CPT_PAN /= 0 then    
            CPT_PAN <= CPT_PAN - 1; -- Line to be commented to synthesize
        end if;
    end if;
end if;
end process;     
end Behavioral;

Answer 1

Which synthesis tool? It would be useful to know.

Xilinx XST 14.3 simply reports <sys_clk> is not declared. and exits.

Add an input port for it, and it synthesises correctly, producing no hardware!

Add an output,

entity Interpretor is
Port (
    SYS_CLK   : in std_logic;
    SCAN_CODE : IN STD_LOGIC_VECTOR(7 downto 0);
    Zero      : Out Boolean
 );
end Interpretor;

and a line to the architecture

Zero <= CPT_Pan = 0;

and it generates pretty much what you would expect. It still optimises away to nothing since CPT_Pan is initialised to 0, and that case is not handled at all by the process.

Dare I ask if you simulated this before trying to synthesise?