I'm trying to simulate my VHDL code using Xilinx ISim.
When I try to generate the testbench for the simulation, the simulator throws up the following error:
FATAL_ERROR:Simulator:Fuse.cpp:500:1.133 - Failed to compile generated C file isim/
I tried to simulate it on an 32-bit Ubuntu 12.04 using ISE 14.3, a 32-bit Windows XP SP3 also ISE 14.3 and a 64-bit Windows 7 SP1 same ISE version as before.
The Xilinx support provided a reinstall as solution, but that didn't solve the problem.
Maybe the community on Stack Overflow has an idea?
That is a tool crash and it's going to be hard to get an answer here on stackoverflow, at least without providing some code and the steps that cause the problem. I would get back with Xilinx support and open a case -- this is something they need to fix in the tool. Can you provide your code as a testcase to them? Potentially cutting it down so it's as simple as possible while still causing the problem.
I can never provide production code to EDA vendors as a testcase due to confidentiality. Quite often I find that while creating a smaller testcase that I can send that I'm able to also find a workaround to the original problem. Try a binary search procedure -- remove or black box half of your design and see if the crash still happens.
And -- can you find the particular C file that fails to compile? Looking at it may give a clue as to what in your design may be causing the problem.