It's common knowledge that many CPU architectures (ARM, PPC) can not read odd addresses but will generate an exception if forced too, and yet others can, but do so slightly slower. (x86)
But is there any CPU which can only address full 32 bit (or even larger!) words? I.e. it can not address 16 bit words? Perhaps amd64?
I am trying to write a portable yet fast C malloc like allocator and want to align my memory accesses properly. Currently I am targeting ARM, i386 and amd64, and these I could look up characteristics for but thought it would be nice to keep an eye open.
I guess a concrete way to put my question would be;
is there a CPU were reading 16 bits from address 0x2 (assuming for the sake of the argument that the address range near 0 is valid in general, I know some CPUs do not use the first page) would give a bus error, where CPU = any of MIPS, ARM, x86, amd64, 68k, 88000, SH, OpenRISC, Sparc, PPC, Cell/SPE?
(I am looking at this whole thing from a C programmer's point of view, by the way. So I assume the C compiler gives me all the normal C types, like char, uint32_t etc.)
Cell's SPEs only have 16-byte quad-word load/store, and those must be aligned on 16-byte boundaries.
If you need to address at finer granularity, you have to read-modify-write, and use bit-masks to only update the relevant parts of the data.
Obviously in C/C++ the compiler will assist with that, and there is support in the instruction set for generating and using masks.
For your example of reading 16-bits from address '2', you would have to read 128-bits from address '0' and mask out the bits you need. If you wanted to write 16-bits to address '2', you would need to read all 128-bits first, then update the appropriate 16-bits, and write the whole lot back.