I'm porting a driver to the 3.4 kernel, and when I do a make clean, it is not cleaning some .o files, so now I'm wondering what the proper way of doing this is.
I have the following Makefile (note: in a separate directory from the kernel):
obj-y += foo.o
foo-objs += foo1.o foo2.o
clean-files := foo3.o
When I run the make clean, it wipes out foo3.o, but leaves foo.o, foo1.o, and foo2.o. I could put all of these into clean-files, but this seems redundant, and I would think that there would be some way to make the Makefile automatically wipe out all objects in obj-y directory.
Thanks,
John
You can use regular expressions in makefiles, and write *.o instead of foo1.o, foo2.o, etc.
Common way is to have a 'clean' target, which looks like this:
clean:
$(RM) .*.cmd *.o *.ko -r .tmp*