I need to do operations on IEEE 754 floating point numbers stored as std_logic_vector
signals.
e.g.:
signal a, b, ans : std_logic_vector( 63 downto 0 );
..
ans <= std_logic_vector(to_float(a) + to_float(b));
How can I do that? (I suppose I need to define the number of bits somewhere during the conversion?) edit: the code is synthesizable but I get warnings. Code:
variable tempfloat1, tempfloat2, tempfloat3 : float32;
..
tempfloat1 := to_float(s_do_ssc2wb, exponent_width => 8, fraction_width => 23 );
tempfloat2 := to_float(s_do_wb2ssc, exponent_width => 8, fraction_width => 23 );
tempfloat3 := tempfloat1 + tempfloat2;
Warnings:
"float_pkg_c.vhdl" line 1515: VHDL Assertion Statement with non constant condition is ignored.
"float_pkg_c.vhdl" line 1600: Index value(s) does not match array range, simulation mismatch.
I wonder whats the right syntax for it... the "add" function doesn't accept the arguments like in the example in the user's guide.
For VHDL 2008, use the built-in float_pkg which provides the float type which is convertable to and from std_logic_vector. For earlier versions of VHDL, you can use the original, pre-standard version of these same packages from http://www.vhdl.org/fphdl/index.html .
When using float types, they work very straightforwardly, similar to unsigned types: you can do arithmetic on them, resize them, etc.