Is there any free program out there that can parse a collection of VHDL files and build a block diagram from them?
I'm looking more for a program that will build a block diagram image to go along with the documentation for the hierarchy, similar to the way javadoc builds a class diagram after parsing the documentation for a series of classes.
There's nothing open-sourced anyways. A while back, I looked for something simliar for verilog designs with no success.