Trouble using 'generate' in verilog always block

I am try to generate some conditions in a case statement in Verilog.

I have a parameter known as MANT_WIDTH and the number of conditions in the case statement depends on the value of MANT_WIDTH

for example I have

always @(*) begin
  case (myvariable)
   {MANT_WIDTH{1'b1}}:
   begin  new_variable = {1'b0, {MANT_WIDTH{1'b1}}};       end

   genvar n;
   generate
     for (n = 2; n <= MANT_WIDTH-1; n = n+1) begin: NORMALIZE
       {(MANT_WIDTH-n){1'b0}},{n{1'b1}}}:
       begin new_variable = {{n{1'b1}},1'b0;
     end


   endgenerate


   default:
   begin  new_variable = {(MANT_WIDTH+1){1'b0}};           end
 endmodule
end

there might be some conditions in this code that don't make sense (incorrect bit widths, etc.) but the gist of what I am trying to do is here.

The problem I am having is that I am getting the following errors when I try to simulate this code using ncverilog:

     for (n = 2; n <= MANT_WIDTH-1; n = n+1) begin: NORMALIZE
          |

ncvlog: *E, ILLPRI (fpmodule.v,278|6): illegal expression primary [4.2(IEEE)]

also I get illegal lvalue syntax [9.2[IEEE)]

I need to count leading zeros. I didn't actually paste my real code, I just need some way to count leading zeros, but I have a few special cases that will have to put outside of a for loop.

THANK YOU SO MUCH!

Solution

I resorted to using the following compiler directives:

`ifdef
`else
`endif

So therefore I could define a block a code as such:

`define MYMACRO 1;

`ifdef MYMACRO

// some code

`else
 `ifdef ANOTHERMACRO
// different code
`endif
`endif