My outputs in 4bits fullAdder are always z and don't change...

I have the following errors appearing on my code, I don't know what they mean neither know how t...

cocotb simulation with Aldec...

Output array won't take the value of an array register...

MachX03 library error in Active-hdl for fpga simulation...

Can not use component in active -hdl 10...

How to use microsoft visual studio as default text editor in Active-hdl...

SystemVerilog stringify (`") operator and line breaks...

Elevator project in VHDL compiles, but doesn't work in the simulation...

understanding of vhdl code and flow of 4 bit ALU?...

RTL simulation of FIFO module by Active HDL (on Lattice Diamond)...